DRAM semiconductor device and method for fabricating the same

ABSTRACT

Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod for fabricating the same, and more particular to, a Dynamic RAM(DRAM) semiconductor device and a method for fabricating the same.

[0003] 2. Description of the Related Art

[0004] In general, as the integration concentration of DRAMsemiconductor devices increases, it is desirable to form source/drainregions as shallow junction regions so as to ensure stability of atransistor. Also, it is required to form contacts having low resistanceto source/drain regions in order to achieve high-speed operation of thetransistor.

[0005] First, a conventional method for fabricating a DRAM semiconductordevice having source/drain regions formed as shallow junction regionsand low-resistance contacts will be described.

[0006]FIGS. 1 through 3 are views for explaining a method forfabricating a DRAM semiconductor device according to the conventionalart. More specifically, FIGS.1 through 3 are views of cell regions ofthe DRAM semiconductor device.

[0007] Referring to FIG. 1, a gate stack pattern 18 on a semiconductorsubstrate 10 in which a Trench Isolation Region (TIR) and a ActiveRegion (AR) has been determined is formed. A silicon substrate is usedfor the semiconductor substrate 10. The gate stack pattern 18 is formedby sequentially stacking a gate electrode constructed with a gatedielectric film (not shown), a poly-silicon film 12 and a metal silicidefilm 14, and a capping film 16. The gate stack pattern 18 functions as aword line.

[0008] Next, an n− source/drain region 20 is formed in the AR of thesemiconductor substrate 10 to be aligned with the gate stack pattern 18.The n− source/drain region 20 is formed as a shallow junction region byion implantation with a shallow implantation depth and a lowconcentration of impurities by using n-type dopants such as phosphorus(P) or arsenic (As), if the semiconductor substrate 10 is a p-typesilicon substrate.

[0009] After the formation of the n− source/drain region 20, a gatespacer 22 is formed on both sidewalls of the gate stack pattern 18. Thenan interlayer dielectric film 24 is formed on the semiconductorsubstrate 10 so as to insulate the gate stack pattern.

[0010] Referring to FIG. 2, the interlayer dielectric film 24 ispatterned by photolithography. Then an interlayer dielectric filmpattern 24 a having a contact hole 26 exposing the n− source/drainregion 20 is formed.

[0011] Referring to FIG. 3, a barrier film 28 formed of Ti/TiN is formedon the wall of the contact hole 26. Then, pads 30 a and 30 b of atungsten film are formed on the barrier film 28. The pad 30 a isconnected to a storage electrode during a subsequent process and the pad30 b is connected to a bit line during the subsequent process. Afterthat, a DRAM semiconductor device is completed through a generalprocesses such as a bit line forming process and a capacitor formingprocess or the like.

[0012] As described above, in a conventional method for fabricating aDRAM semiconductor device, a titanium silicide film is formed by areaction of the n− source/drain region with the Ti film constituting thebarrier film during a thermal process after the barrier film formingprocess. The Ti silicide film penetrates into the n− source/drain regionso that the n− source/drain region is not able to become a shallowjunction region and leakage current is increased during operation of theDRAM semiconductor device.

SUMMARY OF THE INVENTION

[0013] It is an object of the present invention to provide a DRAMsemiconductor device having a source/drain region as a shallow junctionregion and a contact having a low resistance.

[0014] It is another object of the present invention to provide a methodfor fabricating the DRAM semiconductor device.

[0015] In one aspect, the present invention provides a DRAMsemiconductor device comprising a gate stack pattern formed on asemiconductor substrate, a source/drain region which is aligned withboth sidewalls of the gate stack pattern and formed on the semiconductorsubstrate, a gate spacer formed on both sidewalls of the gate stackpattern, a silicon epitaxial layer formed on the source/drain region onboth sides of the gate spacer, a metal silicide layer formed on thesilicon epitaxial layer and a metal pad formed on the metal silicidelayer.

[0016] Preferably, the source/drain region is an n− source/drain region.

[0017] In another aspect, the present invention provides a DRAMsemiconductor device comprising a gate stack pattern formed on a cellregion and a peripheral circuit region of a semiconductor substrate, an− source/drain region which is aligned with both sidewalls of the gatestack pattern of the cell region and formed on the semiconductorsubstrate, a n+ source/drain region and a p+ source/drain region whichis aligned with both sidewalls of the gate stack pattern of theperipheral circuit region and formed on the semiconductor substrate, agate spacer formed on both sidewalls of the gate stack pattern of thecell region and the peripheral circuit region, a silicon epitaxial layerformed on the n− source/drain region, the n+ source/drain region and thep+ source/drain region of a lower portion of both sides of the gatespacer, a metal silicide layer formed on the silicon epitaxial layer ofthe cell region and the peripheral circuit region, a metal pad formed onthe metal silicide layer of the cell region and a metal plug formed onthe metal suicide layer of the peripheral circuit region.

[0018] Preferably, the metal pad is level with equivalent to or higherthan the gate stack pattern. The metal silicide layer is one of a cobaltsilicide layer, a titanium silicide layer and a nickel silicide layer.The metal pad and the metal plug are constructed with a tungsten film.

[0019] In another aspect, the present invention provides a method forfabricating a DRAM semiconductor device comprising forming a gate stackpattern on a semiconductor substrate, forming a source/drain region onthe semiconductor substrate, which is aligned with both sidewalls of thegate stack pattern, forming a silicon epitaxial layer on thesource/drain region of both sidewalls of the gate spacer, forming ametal silicide layer on the silicon epitaxial layer and forming a metalpad on the metal silicide layer.

[0020] In another aspect, the present invention provides a method forfabricating a DRAM semiconductor device comprising forming a gate stackpattern on a cell region and a peripheral circuit region of asemiconductor substrate, forming a n− source/drain region on thesemiconductor substrate of the cell region, to be aligned with bothsidewalls of the gate stack pattern of the cell region, and forming a n+source/drain region and a p+ source/drain region on the semiconductorsubstrate of the peripheral circuit region, forming a gate spacer onboth sidewalls of the gate stack pattern of the cell region and theperipheral circuit region, forming a silicon epitaxial layer on the n−source/drain region, the n+ source/drain region and the p+ source/drainregion of a lower portion of both sides of the gate spacer, forming ametal silicide layer on the silicon epitaxial layer of the cell regionand the peripheral circuit region, forming a metal pad on the metalsilicide layer of the cell region and forming a metal plug on the metalsilicide layer of the peripheral circuit region.

[0021] Preferably, the metal pad is level with or higher than the gatestack pattern. The metal silicide layer is one of a cobalt silicidelayer, a titanium silicide layer and a nickel silicide layer.Preferably, the metal pad and the metal plug are a tungsten film. Thesource/drain regions are the n− source/drain regions. The siliconepitaxial layer is formed by using selective epitaxial growth.

[0022] The DRAM semiconductor device according to the present inventionhas a raised active region formed on the source/drain region of a cellregion and a peripheral circuit region so that the source/drain regioncan be formed as a shallow junction region and the occurrence of leakagecurrent can be reduced.

[0023] In addition to the foregoing, in the DRAM semiconductor device ofthe present invention, a metal silicide layer and a metal pad are formedon a silicon epitaxial layer in the source/drain region of the cellregion and the peripheral circuit region, thereby reducing a contactresistance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above objects and advantages of the present invention willbecome more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

[0025]FIGS. 1 through 3 are views for explaining a conventional methodfor fabricating a DRAM semiconductor device; and

[0026]FIGS. 4A through 4F and 5A through 5F are views for explaining aDRAM semiconductor device and a method of fabricating the DRAMsemiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027] The present invention now will be described more fully withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the invention to those skilled in the art. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity. It will also be understood that when a layer is referred to asbeing “on” another layer or substrate, it can be directly on the otherlayer or substrate, or intervening layers may also be present.

[0028]FIGS. 4F and 5F are sectional views of a cell region and aperipheral circuit region of the DRAM semiconductor device according tothe present invention.

[0029] Specifically, an n-MOS (Metal Oxide Semiconductor) transistor isformed in the cell region of the DRAM semiconductor device as shown inFIG. 4F. As shown in FIG. 5F, in the other regions excluding the cellregion, i.e., the peripheral circuit region of the DRAM semiconductordevice. An n-MOS transistor and p-MOS transistor are formed. However,either n-MOS transistors or p-MOS transistors may be formed in theperipheral circuit region of the DRAM semiconductor device, ifnecessary.

[0030] More specifically, the DRAM semiconductor device according to thepresent invention includes a semiconductor substrate 100 having anActive Region (AR) and a Trench Isolation Region (TIR). Thesemiconductor substrate 100 is a p-type silicon substrate. The TIR isconstructed of a trench by etching the semiconductor substrate 100 and aburied oxide film.

[0031] A gate stack pattern 108 is formed on the semiconductor substrate100 having the AR and the TIR. The gate stack pattern 108 is constructedwith a gate dielectric film (not shown), gate electrodes 102 and 104 anda capping film 106. The gate dielectric film is constructed with anoxide film. The gate electrodes 102 and 104 are constructed with apoly-silicon film 102 and a tungsten suicide film 104. The capping film106 is a nitride film.

[0032] As shown in FIG. 4F, on the AR of the cell region of thesemiconductor substrate 100 of the cell region, an n− source/drainregion 110 aligned with the gate stack pattern 108 is formed. The n−source/drain region 110 of the cell region is constructed as a shallowjunction region. As shown in FIG. 5F, n+ source/drain region 112 and p+source/drain region 114 aligned with the gate stack pattern 108 on theactive region (AR) of the semiconductor substrate 100 of the peripheralcircuit region are formed.

[0033] A gate spacer 116 is formed on both sidewalls of the gate stackpattern 108 of the cell region and the peripheral circuit region. Thegate spacer 116 is constructed with the nitride film. A siliconepitaxial layer 118 is selectively formed on the n− source/drain region110, the n+ source/drain region 112 and the p+ source/drain region 114at both sides of the gate spacer 116 of the cell region and theperipheral circuit region, so as to construct a raised active region.

[0034] The silicon epitaxial layer 118 makes it possible to form ashallow junction and reduces the occurrence of leakage current bypreventing damage to the n− source/drain region 110 in a subsequentthermal process. The silicon epitaxial layer 118 of the cell region andthe peripheral circuit region prevents the metal silicide layer frompenetrating into the n− source/drain region 110, the n+ source/drainregion 112 and the p+ source/drain region 114 in a subsequent thermalprocess, thereby reducing the occurrence of leakage current.

[0035] A metal silicide layer 120 is formed on the silicon epitaxiallayer 118 of the cell region and the peripheral circuit region. Themetal silicide layer 120 may be a cobalt silicide layer, a titaniumsilicide layer or a nickel silicide layer. The metal silicide layer 120lowers a contact resistance when a bit line, a storage electrode of acapacitor and a wiring layer are connected to the n− source/drainregion, the n+ source/drain region and the p+ source/drain region,respectively, during a subsequent process.

[0036] Barrier films 124 and 130 formed of a Ti/TiN film are formed onthe metal silicide layer 120 of the cell region and the peripheralcircuit region, respectively. The metal pads 126 a and 126 b are formedon the barrier film 124 of the cell region. A metal plug 132 is formedon the barrier film 130 of the peripheral circuit region. The metal pad126 a is connected to the storage electrode of the capacitor. The metalpad 126 b is connected to the bit line. The metal pads 126 a and 126 band the metal plug 132 are level with or higher than the gate stackpattern 108. The metal pads 126 a and 126 b and the metal plug 132 areconstructed with the tungsten film. The metal pads 126 a and 126 b andthe metal plug 132 lower a contact resistance when a bit line, a storageelectrode of a capacitor and a wiring layer are connected to the n−source/drain region, the n+ source/drain region and the p+ source/drainregion, respectively, during a subsequent process. The referencenumerals 128 and 128 a of FIGS. 4F and 5F denote an interlayerdielectric film.

[0037] Hereinafter, a method for fabricating a DRAM semiconductor deviceaccording to the present invention will be described.

[0038]FIGS. 4A through 4F and 5A through 5F are sectional views forexplaining a method of fabricating a DRAM semiconductor device accordingto the present invention. FIGS. 4A through 4F are views of a method forfabricating a cell region of a DRAM semiconductor device according tothe present invention. FIGS. 5A through 5F are views of a method formanufacturing of a peripheral circuit region of a DRAM semiconductordevice according to the present invention.

[0039] Referring to FIGS. 4A and 5A, the gate stack pattern 108 isformed on the semiconductor substrate 100 having the AR and the TIR. Thesilicon substrate is used as the semiconductor substrate 100. The gatestack pattern 108 is constructed with the gate dielectric film (notshown), the gate electrodes 102 and 104 and the capping film 106. Thegate dielectric film is an oxide film. The gate electrodes 102 and 104are formed of a poly-silicon film and a tungsten silicide film. Thecapping film 106 is an nitride film.

[0040] Next, the n− source/drain region 110 aligned with the gate stackpattern 108 is formed on the AR of the cell region of the semiconductorsubstrate 100 of the cell region as shown in FIG. 4A. The n−source/drain region 110 is formed as a shallow junction region by an ionimplantation with a shallow implantation depth and a low concentrationof impurities by using n-type dopants such as phosphorus (P) or arsenic(As), if the semiconductor substrate 100 is a p-type silicon substrate.A concentration of the dopants in the n− source/drain region 110 isadjusted to 1E18/cm³-1E20/cm³.

[0041] After that, the n+ source/drain region 112 and the p+source/drain region 114 aligned with the gate stack pattern 108 areformed on the active region (AR) of the semiconductor substrate 100 ofthe peripheral circuit region as shown in FIG. 5A. The n+ source/drainregion 112 is formed with n-type dopants such as phosphorus (P) orarsenic (As) if the semiconductor substrate 10 is a p-type siliconsubstrate. A concentration of the dopants in the n− source/drain region110 is adjusted to 1E20/cm³-1E22/cm³. The p+ source/drain region 114 isformed by the p-type dopants such as boron if the semiconductorsubstrate 10 is a p-type silicon substrate. A concentration of thedopants in the p+ source/drain region 114 is adjusted to1E20/cm³-1E22/cm³.

[0042] Then, a gate spacer 116 is formed on both sidewalls of the gatestack pattern 108 of the cell region and the peripheral circuit region.The gate spacer 116 is formed by forming a nitride film on the wholesurface of the semiconductor substrate 100 in which the gate stackpattern 108 is formed, and anisotropically etching the nitride film 100.

[0043] Referring FIGS. 4B and 5B, the silicon epitaxial layer 118 isselectively formed on the n− source/drain region 110 of the cell region,the n+ source/drain region 112 and the p+ source/drain region 114 of theperipheral circuit region by Selective Epitaxial Growth (SEG), so as toconstruct a raised active region. The silicon epitaxial layer 118 of thecell region makes it possible to form a shallow junction and reduce theoccurrence of leakage current by preventing damage to the n−source/drain region 110 in a subsequent thermal process. The siliconepitaxial layer 118 of the cell region and the peripheral circuit regionprevents the metal silicide layer from penetrating into the n−source/drain region 110, the n+ source/drain region 112 and the p+source/drain region 114 in the subsequent thermal process, therebyreducing the occurrence of leakage current.

[0044] Referring FIGS. 4C and 5C, the metal silicide layer 120 is formedon the silicon epitaxial layer 118 of the cell region and the peripheralcircuit region. The metal silicide layer 120 may be a cobalt silicidelayer, a titanium silicide layer or a nickel silicide layer. The metalsilicide layer 120 lowers a contact resistance when the bit line and thestorage electrode of the capacitor are connected to the n− source/drainregion 110, the n+ source/drain region 112 and the p+ source/drainregion 114 in a subsequent process.

[0045] The metal silicide layer 120 is formed by a self-aligned silicideprocess. In other words, the metal silicide layer 120 is constructed byforming a metal layer on the whole surface of the semiconductorsubstrate 100 in which the cell region and the peripheral circuit regionare formed, applying a thermal process and then a silicidation process.In the silicidation process, the silicon epitaxial layer 118 functionsas a protection layer to prevent damage to the n− source/drain region110, the n+ source/drain region 112 and the p+ source/drain region 114.

[0046] Referring to FIGS. 4D and 5D, a first interlayer dielectric film122 is formed on the whole surface of the cell region and the peripheralcircuit region of the semiconductor substrate in which the gate stackpattern 108 and the metal silicide layer 120 are respectively formed.Then, as illustrated in FIG. 4D, the interlayer dielectric film 122 ofthe cell region is patterned by photolithography to form the interlayerdielectric film 122 a, which has a contact hole 123 exposing the metalsilicide layer 120 of the cell region.

[0047] Referring to FIGS. 4E and 5E, a barrier film 124 formed of Ti/TiNis formed on the whole surface of the cell region and the peripheralcircuit region of the semiconductor substrate 100. Then, a metal layer,e.g., a tungsten film, is formed on the whole surface of the cell regionof the semiconductor substrate 100 to fill the contact hole 123 and theperipheral circuit region, and metal pads 126 a and 126 b are formed byplanarizing the semiconductor substrate 100. A chemical mechanicalpolishing method or an etch back method is used for the planarization.When performing the planarization, a surface of an upper portion of thegate stack pattern 108 can be used for an etching stop point. The metalpads 126 a and 126 b are level with or higher than the gate stackpattern 108.

[0048] The metal pads 126 a and 126 b lower the contact resistance whenthe n− source/drain region 110 is connected to the bit line or thestorage electrode. The metal pad 126 a is connected to the storageelectrode in a subsequent process. The metal pad 126 b is connected tothe bit line in the subsequent process.

[0049] Referring to FIGS. 4F and 5F, a second interlayer dielectric film128 is formed on the whole surface of the semiconductor substrate 100 ofthe cell region and the peripheral circuit region. Then, the secondinterlayer dielectric film 128 is patterned to form a second interlayerdielectric film pattern 128 a to expose the metal silicide layer 120 ofthe peripheral circuit region. After that, a barrier layer 130, e.g.,Ti/TiN film, a metal layer, e.g., a tungsten film, are formed on thewhole surface of the semiconductor substrate 100 and the metal layer isplanarized to from a metal plug 132. When performing the planarization,a surface of an upper portion of the gate stack pattern 108 can be usedfor an etching rest point. The metal plug 132 is level with the gatestack pattern 108. The metal plug 132 lowers the contact resistance whenthe n+ source/drain region 112 and the p+ source/drain region 114 areconnected to a wiring layer in a subsequent process. After that, thesecond interlayer dielectric film 128 of the cell region is patternedand, eventually, a DRAM semiconductor device is completed throughgeneral processes such as a bit line forming process and a capacitorforming process or the like, in which the metal pads 126 a and 126 b areconnected to a bit line or a storage electrode of a capacitor.

[0050] As can be seen from the above, the silicon epitaxial layer isformed on a cell region and a source/drain region of a peripheralcircuit region using SEG, so as to construct a raised active region. Bydoing this, it is possible to form a source/drain region as a shallowjunction region in a cell region and to reduce the occurrence of leakagecurrent by preventing a metal silicide layer from penetrating into thesource/drain region in the cell region and the peripheral circuit regionin a subsequent process.

[0051] In the DRAM semiconductor device according to the presentinvention, a metal silicide layer and a metal pad are formed on asilicon epitaxial layer on the source/drain region of the cell region,and therefore, it is possible to lower a contact resistance between thesource/drain region and the bit line or the storage electrode.

[0052] In addition to the foregoing, in the DRAM semiconductor device ofthe present invention, a metal suicide layer and a metal plug are formedon a silicon epitaxial layer in the source/drain region of the cellregion and the peripheral circuit region thereby reducing the contactresistance between the source/drain region and a wiring layer.

[0053] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A DRAM semiconductor device comprising: a gatestack pattern formed on a semiconductor substrate: a source/drain regionwhich is aligned with both sidewalls of the gate stack pattern andformed on the semiconductor substrate; a gate spacer formed on bothsidewalls of the gate stack pattern; a silicon epitaxial layer formed onthe source/drain region on both sides of the gate spacer; a metalsilicide layer formed on the silicon epitaxial layer; and a metal padformed on the metal silicide layer.
 2. The DRAM semiconductor device ofclaim 1, wherein the metal pad is level with or higher than the gatestack pattern.
 3. The DRAM semiconductor device of claim 1, wherein themetal silicide layer is one of a cobalt silicide layer, a titaniumsilicide layer and a nickel silicide layer.
 4. The DRAM semiconductordevice of claim 1, wherein the metal pad is constructed with a tungstenfilm.
 5. The DRAM semiconductor device of claim 1, wherein thesource/drain region is an n− source/drain region.
 6. A DRAMsemiconductor device comprising: a gate stack pattern formed on a cellregion and a peripheral circuit region of a semiconductor substrate; an− source/drain region which is aligned with both sidewalls of the gatestack pattern of the cell region and formed on the semiconductorsubstrate; a n+ source/drain region and a p+ source/drain region whichis aligned with both sidewalls of the gate stack pattern of theperipheral circuit region and formed on the semiconductor substrate; agate spacer formed on both sidewalls of the gate stack pattern of thecell region and the peripheral circuit region; a silicon epitaxial layerformed on the n− source/drain region, the n+ source/drain region and thep+ source/drain region of a lower portion of both sides of the gatespacer; a metal suicide layer formed on the silicon epitaxial layer ofthe cell region and the peripheral circuit region; a metal pad formed onthe metal silicide layer of the cell region; and a metal plug formed onthe metal silicide layer of the peripheral circuit region.
 7. The DRAMsemiconductor device of claim 6, wherein the metal pad is level withequivalent to or higher than the gate stack pattern.
 8. The DRAMsemiconductor device of claim 6, wherein the metal silicide layer is oneof a cobalt silicide layer, a titanium silicide layer and a nickelsilicide layer.
 9. The DRAM semiconductor device of claim 6, wherein themetal pad and the metal plug are constructed with a tungsten film.
 10. Amethod for fabricating a DRAM semiconductor device, the methodcomprising: forming a gate stack pattern on a semiconductor substrate;forming a source/drain region on the semiconductor substrate, which isaligned with both sidewalls of the gate stack pattern; forming a siliconepitaxial layer on the source/drain region of both sidewalls of the gatespacer; forming a metal silicide layer on the silicon epitaxial layer;and forming a metal pad on the metal silicide layer.
 11. The method ofclaim 10, wherein the metal pad is level with or higher than the gatestack pattern.
 12. The method of claim 10, wherein the metal silicidelayer is one of a cobalt silicide layer, a titanium silicide layer and anickel silicide layer.
 13. The method of claim 10, wherein the metal padand the metal plug are constructed with a tungsten film.
 14. The methodof claim 10, wherein the source/drain region is an n− source/drainregion.
 15. The method of claim 10, the silicon epitaxial layer isformed by using selective epitaxial growth.
 16. A method for fabricatinga DRAM semiconductor device, the method comprising: forming a gate stackpattern on a cell region and a peripheral circuit region of asemiconductor substrate; forming a n− source/drain region on thesemiconductor substrate of the cell region, to be aligned with bothsidewalls of the gate stack pattern of the cell region, and forming a n+source/drain region and a p+ source/drain region on the semiconductorsubstrate of the peripheral circuit region; forming a gate spacer onboth sidewalls of the gate stack pattern of the cell region and theperipheral circuit region; forming a silicon epitaxial layer on the n−source/drain region, the n+ source/drain region and the p+ source/drainregion of a lower portion of both sides of the gate spacer; forming ametal silicide layer on the silicon epitaxial layer of the cell regionand the peripheral circuit region; forming a metal pad on the metalsilicide layer of the cell region; and forming a metal plug on the metalsilicide layer of the peripheral circuit region.
 17. The method of claim16, wherein the metal pad is level with or higher than the gate stackpattern.
 18. The method of claim 16, wherein the metal silicide layer isone of a cobalt silicide layer, a titanium silicide layer and a nickelsilicide layer.
 19. The method of claim 16, wherein the metal pad andthe metal plug are a tungsten film.
 20. The method of claim 16, thesilicon epitaxial layer is formed by using selective epitaxial growth.